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functional block diagram vco data input ad800/AD802 c d retimed data output frac output loop filter det f det ? compensating zero recovered clock output retiming device rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a clock recovery and data retiming phase-locked loop ad800/AD802* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product description the ad800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on non-return to zero, nrz, data. this architecture is capable of supporting data rates between 20 mbps and 160 mbps. the products described here have been defined to work with standard telecommunications bit rates. 45 mbps ds-3 and 52 mbps sts-1 are supported by the ad800-45 and ad800-52 respectively. 155 mbps sts-3 or stm-1 are supported by the AD802-155. unlike other pll-based clock recovery circuits, these devices do not require a preamble or an external vcxo to lock onto input data. the circuit acquires frequency and phase lock using two control loops. the frequency acquisition control loop initially acquires the clock frequency of the input data. the phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. the loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. the devices exhibit 0.08 db jitter peaking, and acquire lock on random or scrambled data within 4 10 5 bit periods when using a damping factor of 5. features standard products 44.736 mbpsds-3 51.84 mbpssts-1 155.52 mbpssts-3 or stm-1 accepts nrz data, no preamble required recovered clock and retimed data outputs phase-locked loop type clock recoveryno crystal required random jitter: 20 8 peak-to-peak pattern jitter: virtually eliminated 10kh ecl compatible single supply operation: C5.2 v or +5 v wide operating temperature range: C40 8 c to +85 8 c during the process of acquisition the frequency detector provides a frequency acquisition (frac) signal which indicates that the device has not yet locked onto the input data. this signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. once the circuit has acquired frequency lock no pulses occur at the frac output. the inclusion of a precisely trimmed vco in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components. the vco provides a clock output within 20% of the device center frequency in the absence of input data. the ad800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. total loop jitter is 20 peak-to-peak. jitter bandwidth is dictated by mask programmable fractional loop bandwidth. the ad800, used for data rates < 90 mbps, has been designed with a nominal loop bandwidth of 0.1% of the center frequency. the AD802, used for data rates in excess of 90 mbps, has a loop bandwidth of 0.08% of center frequency. all of the devices operate with a single +5 v or C5.2 v supply. * protected by u.s. patent no. 5,027,085.
rev. b C2C ad800/AD802Cspecifications (v ee = v min to v max , v cc = gnd, t a = t min to t max , loop damping factor = 5, unless otherwise noted) ad800-45bq ad800-52br AD802-155kr/br parameter 1 condition min typ max min typ max min typ max units nominal center frequency 44.736 51.84 155.52 mhz operating temperature k grade 0 70 c range (t min to t max ) b grade C40 85 C40 85 C40 85 c tracking range 43 45.5 49 53 155 156 mbps capture range 43 45.5 49 53 155 156 mbps static phase error r = 1, t a = +25 c, v ee = C5.2 v 2 10 2 10 14 30 degrees r = 1 3 11.5 3 11.5 18 37 degrees recovered clock skew t rcs (figure 1) 0.2 0.6 1 0.2 0.6 1 0.2 0.8 1 ns setup time t su (figure 1) 2.06 2.37 ns transitionless data run 240 240 240 bit periods output jitter r = 1 2 2 3.5 degrees rms 2 7 C1 prn sequence 2.5 4.7 2.5 4.7 5.4 9.7 degrees rms 2 23 C1 prn sequence 2.5 4.7 2.5 4.7 5.4 9.7 degrees rms jitter tolerance f = 10 hz 2,500 2,500 3,000 unit intervals f = 2.3 khz 6.5 unit intervals f = 30 khz 0.47 unit intervals f = 1 mhz 0.47 unit intervals f = 30 hz 830 unit intervals f = 300 hz 83 unit intervals f = 2 khz 7.4 unit intervals f = 20 khz 0.47 unit intervals f = 6.5 khz 2.0 7.6 unit intervals f = 65 khz 0.26 0.9 unit intervals jitter transfer damping factor capacitor, c d z = 1, nominal 8.2 6.8 2.2 nf z = 5, nominal 0.22 0.15 0.047 m f z = 10, nominal 0.82 0.68 0.22 m f peaking z = 1, nominal t a = +25 c, v ee = C5.2 v 2 2 2 db z = 5, nominal t a = +25 c, v ee = C5.2 v 0.08 0.08 0.08 db z = 10, nominal t a = +25 c, v ee = C5.2 v 0.02 0.02 0.02 db bandwidth 45 52 130 khz acquisition time r = 1/2 z = 1 1 10 4 1 10 4 1.5 10 4 bit periods t a = +25 c z = 5 3 10 5 8 10 5 3 10 5 8 10 5 4 10 5 8 10 5 bit periods v ee = C5.2 v z = 10 8 10 5 8 10 5 1.4 10 6 bit periods power supply voltage (v min to v max )t a = +25 c C4.5 C5.2 C5.5 C4.5 C5.2 C5.5 C4.5 C5.2 C5.5 volts current t a = +25 c, v ee = C5.2 v 125 170 125 170 140 180 ma 180 180 205 ma input voltage levels t a = +25 c input logic high, v ih C1.084 C0.72 C1.084 C0.72 C1.084 C0.72 volts input logic low, v ih C1.95 C1.594 C1.95 C1.594 C1.95 C1.594 volts output voltage levels t a = +25 c output logic high, v oh C1.084 C0.72 C1.084 C0.72 C1.084 C0.72 volts output logic low, v ol C1.95 C1.60 C1.95 C1.60 C1.95 C1.60 volts input current levels t a = +25 c input logic high, i ih 125 125 125 m a input logic low, i il 80 80 80 m a output slew times t a = +25 c rise time (t r ) 20%C80% 0.75 1.5 0.75 1.5 0.75 1.5 ns fall time (t f ) 80%C20% 0.75 1.5 0.75 1.5 0.75 1.5 ns symmetry r = 1/2, t a = +25 c recovered clock output v ee = C5.2 v 45 55 45 55 45 55 % notes 1 refer to glossary for parameter definition. specifications subject to change without notice.
ad800/AD802 rev. b C3C absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C6 v input voltage (pin 16 or pin 17 to v cc ) . . . . v ee to +300 mv maximum junction temperature soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150 c ceramic dip package . . . . . . . . . . . . . . . . . . . . . . +175 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . +300 c esd rating ad800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 v AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 v *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to an absolute maximum rating condition for an extended period may adversely affect device reliability. recovered clock skew, t rcs dataout 50% (pin 2) clkout 50% (pin 5) setup time t su figure 1. recovered clock skew and setup (see previous page) pin descriptions number mnemonic description 1 dataout differential retimed data output 2 dataout differential retimed data output 3v cc2 digital ground 4 clkout differential recovered clock output 5 clkout differential recovered clock output 6v ee digital v ee 7v ee digital v ee 8v cc1 digital ground 9av ee analog v ee 10 asubst analog substrate 11 cf 2 loop damping capacitor input 12 cf 1 loop damping capacitor input 13 av cc analog ground 14 v cc1 digital ground 15 v ee digital v ee 16 datain differential data input 17 datain differential data input 18 subst digital substrate 19 frac differential frequency acquisition indicator output 20 frac differential frequency acquisition indicator output thermal characteristics q jc q ja soic package 22 c/w 75 c/w cerdip package 25 c/w 90 c/w use of a heatsink may be required depending on operating environment. glossary maximum and minimum specifications maximum and minimum specifications result from statistical analyses of measurements on multiple devices and multiple test systems. typical specifications indicate mean measurements. maximum and minimum specifications are calculated by adding or subtracting an appropriate guardband from the typical specification. device-to-device performance variation and test system-to-test system variation contribute to each guardband. nominal center frequency this is the frequency that the vco will operate at with no input signal present and the loop damping capacitor, c d , shorted. tracking range this is the range of input data rates over which the pll will remain in lock. capture range this is the range of input data rates over which the pll can acquire lock. static phase error this is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. gate delays between the signals that define static phase error, and ic input and output signals prohibit direct measurement of static phase error. data transition density, r this is a measure of the number of data transitions, from 0 to 1 and from 1 to 0, over many clock periods. r is the ratio (0 r 1) of data transitions to clock periods. jitter this is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms, or unit intervals (ui). jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered clock causes jitter on the retimed data. output jitter this is the jitter on the retimed data, in degrees rms, due to a specific pattern or some psuedo-random input data sequence (prn sequence). jitter tolerance jitter tolerance is a measure of the plls ability to track a jittery input data signal. jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. ordering guide fractional loop device center frequency bandwidth description operating temperature package option ad800-45bq 44.736 mhz 0.1% 20-pin cerdip C40 c to +85 c q-20 ad800-52br 51.84 mhz 0.1% 20-pin plastic soic C40 c to +85 c r-20 AD802-155br 155.52 mhz 0.08% 20-pin plastic soic C40 c to +85 c r-20 AD802-155kr 155.52 mhz 0.08% 20-pin plastic soic 0 c to +70 c r-20
ad800/AD802 rev. b C4C the pll must provide a clock signal which tracks this phase modulation in order to accurately retime jittered data. in order for the vco output to have a phase modulation which tracks the input jitter, some modulation signal must be generated at the output of the phase detector (see figure 21). the modulation output from the phase detector can only be produced by a phase error between the data input and the clock input. hence, the pll can never perfectly track jittered data. however, the magnitude of the phase error depends on the gain around the loop. at low frequencies the integrator provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. at frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. the pll data output will have a bit error rate less than 1 3 10 C10 when in lock and retiming input data that has the specified jitter applied to it. jitter transfer the pll exhibits a low-pass filter response to jitter applied to its input data. bandwidth this describes the frequency at which the pll attenuates sinusoidal input jitter by 3 db. peaking this describes the maximum jitter gain of the pll in db. damping factor, z z describes how the pll will track an input signal with a phase step. a greater value of z corresponds to less overshoot in the pll response to a phase step. z is a standard constant in second order feedback systems. acquisition time this is the transient time, measured in bit periods, required for the pll to lock on input data from its free-running state. symmetry symmetry is calculated as (100 3 on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its 0 level and its 1 level. bit error rate vs. signal-to-noise ratio the ad800 and AD802 were designed to operate with standard ecl signal levels at the data input. although not recom- mended, smaller input signals are tolerable. figure 8, 14, and 20 show the bit error rate performance versus input signal-to- noise ratio for input signal amplitudes of full 900 mv ecl, and decreased amplitudes of 80 mv and 20 mv. wideband ampli- tude noise is summed with the data signals as shown in figure 2. the full ecl and 80 mv signals give virtually indistinguish- able results. the 20 mv signals also provide adequate perfor- mance when in lock, but signal acquisition may be impaired. ? power combiner ? 0.47 m f 50 w 50 w 0.47 m f power combiner 75 w 1.0 m f 180 w power splitter filter noise source 100mhz ?AD802-155 33mhz ?ad800-52 gnd ?.2v d.u.t. ad800/AD802 data in data in differential signal source figure 2. bit error rate vs. signal-to-noise ratio test: block diagram using the ad800 and the AD802 series ground planes use of one ground plane for connections to both analog and digital grounds is recommended. output signal sensitivity to power supply noise (pecl configuration, figure 22) is less using one ground plane than when using separate analog and digital ground planes. power supply connections use of a 10 m f tantalum capacitor between v ee and ground is recommended. use of 0.1 m f ceramic capacitors between ic power supply or substrate pins and ground is recommended. power supply decoupling should take place as close to the ic as possible. refer to schematics, figure 22 and figure 26, for advised connections. sensitivity of ic output signals (pecl configuration, figure 22) to high frequency power supply noise (at 2 3 the nominal data rate) can be reduced through the connection of signals av cc and v cc1 , and the addition of a bypass network. the type of bypass network to consider depends on the noise tolerance required. the more complex bypass network schemes tolerate greater power supply noise levels. refer to figures 23 and 24 for bypassing schemes and power supply sensitivity curves. transmission lines use of 50 w transmission lines are recommended for datain, clkout, dataout, and frac signals. terminations termination resistors should be used for datain, clkout, dataout, and frac signals. metal, thick film, 1% tolerance resistors are recommended. termination resistors for the datain signals should be placed as close as possible to the datain pins. connections from v ee to lead resistors for datain, data- out, frac, and clkout signals should be individual, not daisy chained. this will avoid crosstalk on these signals. loop damping capacitor, c d a ceramic capacitor may be used for the loop damping capacitor. input buffer use of an input buffer, such as a 10h116 line receiver ic, is suggested for an application where the datain signals do not come directly from an ecl gate, or where noise immunity on the datain signals is an issue.
ad800/AD802 rev. b C5C 52 38 100 44 40 ?0 42 ?0 50 46 48 80 60 40 20 0 temperature ? c center frequency ?mhz figure 3. ad800-45 center frequency vs. temperature 52 38 100 44 40 ?0 42 ?0 50 46 48 80 60 40 20 0 temperature ? c data rate ?mbps figure 5. ad800-45 capture and tracking range vs. temperature 55 35 0.30 41 37 0.05 39 0 47 43 45 49 51 53 0.25 0.20 0.15 0.10 input jitter ?ui p-p data rate ?mbps c d = 0.68 m f figure 7. ad800-45 acquisition range vs. input jitter 10 0 100 3 1 ?0 2 ?0 6 4 5 7 8 9 80 60 40 20 0 temperature ? c jitter ?degrees rms figure 4. ad800-45 jitter vs. temperature 100 0.1 10 0 10 6 10 1 10 1 10 5 10 4 10 3 10 2 jitter frequency ?hz unit intervals ?p-p ad800-45 ds-3 mask figure 6. ad800-45 jitter tolerance 1e-5 1e-11 1e-2 10 12 16 18 22 24 1e-3 1e-4 1e-9 1e-7 1e-1 5e-2 3e-2 2e-2 s/n ?db 1 2 erfc s n 1 2 2 14 20 80 20 ecl 20 80 bit error rate figure 8. ad800-45 bit error rate vs. input jitter typical characteristics C
ad800/AD802 rev. b C6C 58 40 100 44 42 ?0 ?0 46 48 50 52 54 56 80 60 40 20 0 temperature ? c center frequency ?mhz figure 9. ad800-52 center frequency vs. temperature 58 40 100 44 42 ?0 ?0 46 48 50 52 54 56 80 60 40 20 0 temperature ? c data rate ?mbps figure 11. ad800-52 capture and tracking range vs. temperature 60 40 0.30 46 42 0.05 44 0 52 48 50 54 56 58 0.25 0.20 0.15 0.10 input jitter ?ui p-p data rate ?mbps c d = 0.68 m f figure 13. ad800-52 acquisition range vs. input jitter 10 0 100 3 1 ?0 2 ?0 6 4 5 7 8 9 80 60 40 20 0 temperature ? c jitter ?degrees rms figure 10. ad800-52 jitter vs. temperature 100 0.1 10 0 10 1 10 1 10 5 10 4 10 3 10 2 jitter frequency ?hz unit intervals ?p-p ad800-52 oc-1 mask figure 12. ad800-52 jitter tolerance 1e-5 1e-10 1e-2 10 12 16 18 22 24 1e-3 1e-4 1e-8 1e-6 1e-1 5e-2 3e-2 2e-2 s/n ?db 1 2 erfc s n 1 2 2 14 20 80 20 ecl 20 80 bit error rate figure 14. ad800-52 bit error rate vs. input jitter
ad800/AD802 rev. b C7C 180 100 120 110 ?0 140 130 150 160 170 100 80 60 40 20 0 ?0 temperature ? c center frequency ?mhz figure 15. AD802-155 center frequency vs. temperature temperature ? c 200 130 100 160 140 ?0 150 ?0 190 170 180 80 60 40 20 0 data rate ?mbps figure 17. AD802-155 capture range, tracking range vs. temperature input jitter ?ui 100 0 1 1000 10 0.1 10 1 100 AD802 ?155 ccitt g.958 stm1 type a mask jitter frequency ?hz figure 19. AD802-155 minimum acquisition range vs. jitter frequency, t min to t max v min to v max 100 ?0 ?0 10 0 3 1 2 6 4 5 7 8 9 80 60 40 20 0 jitter ?degrees rms temperature ? c figure 16. AD802-155 output jitter vs. temperature 100 0.1 10 2 10 1 ui ?pk-pk 10 3 10 4 10 5 10 8 10 7 10 6 jitter frequency ?hz AD802-155 ccitt g.958 stm1 type a mask figure 18. AD802-155 jitter tolerance 1e-5 1e-10 1e-2 10 12 16 18 22 24 1e-3 1e-4 1e-8 1e-6 1e-1 5e-2 3e-2 2e-2 bit error rate s/n ?db 1 2 erfc s n 1 2 2 14 20 80mv 20mv ecl 20mv 80mv & ecl 1e-12 figure 20. AD802-155 bit error rate vs. input jitter
ad800/AD802 rev. b C8C theory of operation the ad800 and AD802 are phase-locked loop circuits for re- covery of clock from nrz data. the architecture uses a fre- quency detector to aid initial frequency acquisition, refer to figure 21 for a block diagram. note the frequency detector is al- ways in the circuit. when the pll is locked, the frequency error is zero and the frequency detector has no further effect. since the frequency detector is always in circuit, no control functions are needed to initiate acquisition or change mode after acquisi- tion. the frequency detector also supplies a frequency acquisi- tion (frac) output to indicate when the loop is acquiring lock. during the frequency acquisition process the frac output is a series of pulses of width equal to the period of the vco. these pulses occur on the cycle slips between the data frequency and the vco frequency. with a maximum density (1010 . . .) data pattern, every cycle slip will produce a pulse at frac. how- ever, with random data, not every cycle slip produces a pulse. the density of pulses at frac increases with the density of data transitions. the probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. after the frequency error has been reduced to zero, the frac output will have no further pulses. at this point the pll begins the process of phase acquisition, with a settling time of roughly 2000 bit pe- riods. valid retimed data can be guaranteed by waiting 2000 bit periods after the last frac pulse has occurred. jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). briefly, the measurement of zero phase error does not cause the vco phase to increase to above the average run rate set by the data frequency. the jitter created by a 2 7 C1 pseudo-random code is 1/2 degree, and this is small compared to random jitter. the jitter bandwidth for the AD802-155 is 0.08% of the center frequency. this figure is chosen so that sinusoidal input jitter at 130 khz will be attenuated by 3 db. the jitter bandwidths of the ad800-45 and ad800-52 are 0.1% of the respective center frequencies. the jitter bandwidth of the ad800 or the AD802 is mask programmable from 0.01% to 1% of the center frequency. a device with a very low loop bandwidth (0.01% of the center frequency) could effectively filter (clean up) a jittery timing reference. consult the factory if your application requires a special loop bandwidth. the damping ratio of the phase-locked loop is user program- mable with a single external capacitor. at 155 mhz a damping ratio of 10 is obtained with a 0.22 m f capacitor. more generally, the damping ratio scales as 1. 7 f data c d . at 155 mhz a damping ratio of 1 is obtained with a 2.2 nf capacitor. a lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. however, at damping ratios approaching one, the acquisition time no longer scales directly with the capacitor value. the acquisition time has two components: frequency acquisition and phase acquisition. the frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the pll and is independent of the damping ratio. thus, the 0.08% fractional loop bandwidth sets a minimum acquisition time of 15,000 bit periods. note the acquisition time for a damping factor of 1 is specified as 15,000 bit periods. this comprises 13,000 bit periods for frequency acquisition and 2,000 periods for phase acquisition. compare this to the 400,000 bit periods acquisition time specified for a damping ratio of 5; this consists entirely of frequency acquisition, and the 2,000 bit periods of phase acquisition is negligible. while lower damping ratio affords faster acquisition, it also allows more peaking in the jitter transfer response (jitter peaking). for example, with a damping ratio of 10 the jitter peaking is 0.02 db, but with a damping factor of 1, the peaking is 2 db. det ts + 1 retiming device vco ? f det data input recovered clock output retimed data output frac output 1 s figure 21. ad800 and AD802 block diagram
ad800/AD802 rev. b C9C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dataout dataout v cc2 clkout clkout av ee asubst frac frac subst datain datain av cc cf 1 cf 2 dataout dataout clkout clkout z1 ad800/802 j1 j2 r1 r2 r5 100 r10 r6 100 5.0v r9 r12 r11 r7 100 r8 100 r3 r4 j3 j4 c10 0.1 100 100 154 154 154 154 100 100 c d r22 80.6 r21 80.6 r19 130 r20 130 frac frac 5.0v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 z2 10h116 r24 130 r23 130 j5 j6 r26 80.6 r25 80.6 datain datain 5.0v 0.1 0.1 0.1 c7 0.1 c6 0.1 0.1 c16 5.0v 5.0v r16 100 5.0v c13 0.1 100 100 154 154 0.1 c20 c21 0.1 5.0v 5.0v c8 c9 0.1 c5 c4 c3 r13 r14 r15 100 r17 r18 c17 0.1 c14 0.1 c15 0.1 0.1 0.1 c12 c11 c19 0.1 v ee c2 10 m f 5.0v bypass network out in v ee v cc1 v ee v cc1 figure 22. evaluation board schematic, positive supply table i. evaluation board, positive supply: components list reference designator description quantity r1C8, r15C18 resistor, 100 w , 1% 12 r9C14 resistor, 154 w , 1% 6 r19, 20, 23, 24 resistor, 130 w , 1% 4 r21, 22, 25, 26 resistor, 80.6 w , 1% 4 c d capacitor, loop damping (see specifications page) 1 c2 capacitor, 10 m f, tantalum 1 c3Cc21 capacitor, 0.1 m f, ceramic chip 17 z1 ad800/AD802 1 z2 10h116, ecl line receiver 1 in 0.1 m f c2 10 m f bypass network (a, b, c, or d) to device in 5.0v beads with one loop in 0.1 m f to device to device (a) in 0.1 m f to device bead with one loop (b) (c) bead with two loops in 0.1 m f to device bead with two loops (d) bead with two loops bypass network components: capacitor ..........ceramic chip ferrite bead......1/4 in. stackpole carbo 57-1392 3.0 0 1.0 1.5 0.5 0.1 1.0 0 2.5 2.0 0.9 0.7 0.6 0.5 0.8 0.4 0.3 0.2 jitter ?ns p-p noise ?v p-p @ 311mhz (a) (b) (c) (d) figure 23. bypass network schemes figure 24. AD802-155 output jitter vs. supply noise (pecl configuration)
ad800/AD802 rev. b C10C bypass network (a, b, c, or d) micro metals t50-10 to device pins 6, 7, 9 10, 15, 18 pins 8, 13, 14 AD802-155 pin 3 in 0.47 m f 0.47 m f 10 turns 10 m f 5v 50 w noise in sense figure 25. power supply noise sensitivity test circuit, pecl configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ?.2v dataout clkout v ee av ee asubst frac subst datain v cc1 av cc cf 1 cf 2 dataout clkout frac datain dataout clkout dataout clkout 1 2 3 4 5 6 7 8 z2 10h116 z1 ad800/802 j1 j2 r1 r2 r5 100 r10 c3 r6 100 ?.2v r9 c4 r12 r11 r7 100 r8 100 r3 r4 j3 j4 ?.2v c5 100 100 154 154 0.1 0.1 154 154 100 100 0.1 c2 10 c6 0.1 c10 0.1 ?.2v c d r14 80.6 r13 80.6 c7 0.1 ?.2v 0.1 r21 274 r22 274 c8 0.1 c9 0.1 r15 130 r16 130 frac ?.2v 16 15 14 13 12 11 10 9 c11 0.1 r20 130 r19 130 j5 j6 r18 80.6 r17 80.6 datain datain ?.2v ?.2v ?.2v c12 v cc2 v ee v ee v cc1 frac figure 26. evaluation board schematic, negative supply table ii. evaluation board, negative supply: components list reference designator description quantity r1C8 resistor, 100 w , 1% 8 r9C12 resistor, 154 w , 1% 4 r13, 14, 17, 18 resistor, 80.6 w , 1% 4 r15, 16, 19, 20 resistor, 130 w , 1% 4 r21, 22 resistor, 274 w , 1% 2 c d capacitor, loop damping (see specifications page) 1 c2 capacitor, 10 m f, tantalum 1 c3Cc12 capacitor, 0.1 m f, ceramic chip 10 z1 ad800/AD802 1 z2 10h116, ecl line receiver 1
ad800/AD802 rev. b C11C figure 27. negative supply configuration: component side (top layer) figure 28. negative supply configuration: solder side figure 29. positive supply configuration: component side (top layer) figure 30. positive supply configuration: solder side
ad800/AD802 rev. b C12C outline dimensions dimensions shown in inches and (mm). 20-pin small outline ic package (r-20) 110 11 20 0.50 (1.27) bsc 0.015 (0.38) 0.007 (0.18) 0.019 (0.48) 0.014 (0.36) 0.011 (0.28) 0.004 (0.10) 0.050 (1.27) 0.016 (0.40) 0.104 (2.64) 0.093 (2.36) 0.419 (10.65) 0.394 (10.00) 0.300 (7.60) 0.292 (7.40) 0.512 (13.00) 0.496 (12.60) 20-pin cerdip package (q-20) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min pin 1 0.098 (2.49) max 0.310 (7.87) 0.220 (5.59) 10 11 1 20 1.060 (26.92) max 0.200 (5.08) max 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane c1725aC7.5C12/93 printed in u.s.a.

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